5-transistor memory cell with known state on power-up

Details 5-transistor memory cell with known state on power-up 5-transistor memory cell with known state on power-up

G - Physics

11

C

352/82.22

G11C 11/41 (2006.01) G11C 7/12 (2006.01) G11C 7/20 (2006.01) G11C 8/08 (2006.01) G11C 11/412 (2006.01)

Patent

CA 1323928

A 5-TRANSISTOR MEMORY CELL WITH KNOWN STATE ON POWER-UP Hung-Cheng Hsieh ABSTRACT A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read, selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to reading. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation. Selective doping of the pull-up transistors of the inverters in the memory cell controls the initial state of the memory cell after the memory cell is powered up.

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