A 0-100% duty cycle, transformer isolated fet driver

H - Electricity – 03 – K

Patent

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Details

H03K 19/0175 (2006.01) H03K 17/61 (2006.01) H03K 17/691 (2006.01)

Patent

CA 2110794

A transformer isolates a control circuit from a FET, the control circuit including a clock generator for providing, when en- abled, a clock signal to the transformer primary. A PWM input selectively disables the clock generator from providing the clock signal to the transformer primary. The transformer secondary is connected in a full wave centertap configuration for providing a full wave rectified version of the clock signal, the full wave rectified version being a relatively constant DC voltage signal suppli- ed at one level to the FET to turn on the FET when the clock generator is enabled to provide the clock signal to the primary. The centertap configuration provides a relatively constant DC voltage signal at a second level to the FET to turn off the FET when the clock generator is disabled by the PWM input from providing the clock signal to the primary.

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