A/d conversion offset error correction

H - Electricity – 03 – M

Patent

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Details

H03M 1/18 (2006.01) H03M 1/06 (2006.01) H03M 1/12 (2006.01)

Patent

CA 2371609

An A/D conversion offset error correction arrangement includes an A/D converter (10) for converting analog signals into digital signals. A decoder (12) decodes the digital signals into binary signals. A converter (20) converts the binary signals into equivalent decoded digital signals. Means (16, 18, 24) are provided for forming an offset error estimate by averaging the difference between the digital signals and the decoded digital signals. An adder (26) subtracts the offset error estimate from future digital signals before these signals are decoded.

L'invention concerne un système de conversion analogique/numérique de correction d'erreur de décalage comprenant un convertisseur A/N (10) destiné à la conversion de signaux analogiques en signaux numériques. Un décodeur (12) décode les signaux numériques en signaux binaires. Un convertisseur (20) convertit les signaux binaires en signaux numériques décodés équivalents. Des moyens (16, 18, 24) permettent de faire une estimation d'erreur de décalage en établissant une moyenne de la différence entre les signaux numériques et les signaux numériques décodés. Un additionneur (26) soustrait l'estimation d'erreur de décalage des futurs signaux numériques avant que ces signaux ne soient décodés.

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