G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 13/20 (2006.01) G06F 13/36 (2006.01) G06F 13/40 (2006.01)
Patent
CA 2255350
This invention provides a data processing apparatus with a hierarchical bus for realizing appropriate data transfer speed and data processing speed, even if more I/O devices are connected to the data processing apparatus. Processor are provided in a part or all of layers in the hierarchical bus. The processors perform a selection, projection, and accumulation processing of data transmitted from I/O devices to a main memory. Accordingly, a data amount transmitted to a system bus at an upper layer can be reduced, and a data amount processed by the CPU can be reduced.
Kirby Eades Gale Baker
Mitsubishi Denki Kabushiki Kaisha
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