A delay line providing an adjustable delay

Details A delay line providing an adjustable delay A delay line providing an adjustable delay

H - Electricity

03

K

328/31

H03K 17/28 (2006.01) H03H 11/26 (2006.01)

Patent

CA 2040134

First and second complementary input voltages control current flow through first and second switches (e.g. semiconductor devices) each respectively connected in first and second control circuits with a first constant current source. When the input voltages change, current starts to increase through one control circuit to produce increases in the voltage drop across an impedance (e.g. resistor) in such circuit. When a particular voltage difference is produced between the impedance voltage and an adjustable biasing voltage, a third switch (e.g. semiconductor device) closes to produce a first resultant voltage. The resultant delay in the third switch closure is dependent upon the adjustable magnitude of the biasing voltage. As the voltage increases across the impedance in the one control circuit, the voltage decreases across an impedance in the other control circuit, causing a second resultant voltage to be produced at a fourth switch (e.g. semiconductor device). The resultant voltages are respectively introduced to fifth and sixth switches (e.g. semiconductor devices) each connected in a circuit with an individual one of second and third constant current sources. When the resultant voltages change, the particular one of the fifth and sixth switches receiving an increase in current passes a portion of this current through the associated current source and another portion of this current through a coupling member and the other current source. This delays the state of non-conductivity of the switch connected to the other current source. Output voltages further delayed from the input voltages are accordingly obtained from the fifth and sixth switches.

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