A digital signal processor reducing access contention

Details A digital signal processor reducing access contention A digital signal processor reducing access contention

G - Physics

06

F

G06F 9/30 (2006.01) G06F 9/38 (2006.01) G06F 15/78 (2006.01)

Patent

CA 2324219

A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

L'invention concerne un circuit de traitement de signaux numériques (DSP) nécessitant un ensemble d'instructions de longueur variable. Un DSP donné en exemple comporte un ensemble de trois bus (108, 110, 112) de données par lesquels des données peuvent être échangées avec un groupe (120) de registres et trois mémoires (102, 103, 104) de données. On peut utiliser un groupe (120) de registres qui comporte des registres accessibles par au moins deux unités (128, 130) de traitement. On peut inclure une unité (156) de prise en charge d'instructions qui reçoit des instructions de longueur variable stockées dans une mémoire (152) d'instructions. La mémoire (152) d'instructions peut être distincte de l'ensemble des trois mémoires (102, 103, 104) de données.

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