A digitally controlled first order jitter attenuator using a...

H - Electricity – 03 – L

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H03L 7/081 (2006.01) H03L 7/085 (2006.01) H03L 7/099 (2006.01)

Patent

CA 2180466

A circuit for attenuating phase jitter on an incoming clock signal includes a digital frequency synthesizer, and a phase lock loop including a phase detector. The digital phase detector compares the phase relationship between an incoming signal and a clock signal generated by the digitally controlled frequency synthesizer and produces an output signal proportional to the phase difference. The output signal comprises both a direction indicator and a magnitude indicator for controlling the digitally controlled frequency synthesizer. One of a plurality of phases of a voltage controlled oscillator (VCO) are selected in response to the output signal to alter the frequency of the clock signal.

Circuit permettant d'atténuer l'instabilité de phase sur un signal d'horloge entrant qui comporte un synthétiseur de fréquences numérique et une boucle à verrouillage de phase comprenant un détecteur de phase. Le détecteur de phase numérique compare la relation de phase entre un signal entrant et un signal d'horloge généré par le synthétiseur de fréquences à commande numérique et produit un signal de sortie proportionnel à la différence de phase. Le signal de sortie comporte à la fois un indicateur de direction et un indicateur de grandeur destinés à commander le synthétiseur de fréquences à commande numérique. L'une des phases d'une pluralité de phases d'un oscillateur commandé en tension (VCO) est sélectionnée en réponse au signal de sortie pour modifier la fréquence du signal d'horloge.

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