A frequency-locked loop with gated reference and vco inputs

Details A frequency-locked loop with gated reference and vco inputs A frequency-locked loop with gated reference and vco inputs

H - Electricity

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H03L 7/097 (2006.01) H03D 11/02 (2006.01) H03D 13/00 (2006.01) H03L 7/083 (2006.01) H03L 7/089 (2006.01) H03L 7/14 (2006.01) H03L 7/18 (2006.01) H04L 27/02 (2006.01) H04L 27/00 (2006.01)

Patent

CA 2260456

Disclosed is a frequency-locked loop (FLL), which attempts to bring about frequency and phase synchronization between two signals over the control bandwidth of the loop: a reference signal and a voltage-controlled oscillator (VCO) signal. A preferred embodiment of the invention employs a reference signal generated by a crystal oscillator of frequency f REF (possibly reduced in frequency by dividing by a factor R), and a VCO signal generated by the oscillations of an unquenched SRG resonator (possibly passed through a limiting amplifier) with tunable resonant frequency f RES (possibly reduced in frequency by dividing by a factor N). These (possibly divided-down) signals are connected to the inputs of a phase/frequency detector (PFD). A PFD a circuit which compares the phases of two digital input signals, denoted "R" and "V" for "reference" and "VCO"; if a reference rising edge precedes a VCO rising edge, an "up" pulse denoted "U" is generated, while a VCO edge preceding a reference edge generates a "down" ("D") pulse. These pulses are used to control the current sources in a charge-pump circuit whose net current is applied to a loop filter (LF) which creates a voltage using some kind of charge-storage element. This loop filter voltage is a so-called error voltage whose value is used to control the frequency of the resonator; the combination of PFD, charge pump, and LF is connected such that the error voltage is controlled to bring the reference signal and VCO signal into phase synchrony.

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