A frequency/phase comparison circuit with gated reference...

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G01R 23/14 (2006.01) H03D 13/00 (2006.01) H03L 7/089 (2006.01) H03L 7/091 (2006.01) H03L 7/099 (2006.01) H03L 7/14 (2006.01) H03L 7/18 (2006.01) H04B 1/26 (2006.01) H04L 27/02 (2006.01) H04L 27/00 (2006.01)

Patent

CA 2290862

Disclosed is a frequency-locked loop (FLL), which attempts to bring about frequency and phase synchronization between two signals over the control bandwidth of the loop: a reference signal and a voltage-controlled oscillator (VCO) signal. For example, the FLL employs a reference signal generated by a crystal oscillator of frequency .function. REF and a VCO signal generated by the oscillations of an unquenched SRG resonator with tunable resonant frequency .function. RES. These signals are connected to the inputs of a phase/frequency detector (PFD) which produces output pulses in response to the relationship between .function.REF and .function.RES. These pulses are applied to a loop filter (LF) which creates a voltage using some kind of charge-storage element. This loop filter voltage is a so-called error voltage whose value is used to control the frequency of the resonator to bring the reference signal and VCO signal into phase synchrony.

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