A gettering method and a wafer using the same

Details A gettering method and a wafer using the same A gettering method and a wafer using the same

H - Electricity

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H01L 21/00 (2006.01) H01L 21/203 (2006.01) H01L 21/328 (2006.01) H01L 21/334 (2006.01) H01L 21/363 (2006.01) H01L 29/66 (2006.01)

Patent

CA 2582632

It is shown in the invention a method for manufacturing a semiconductor wafer structure with an active layer for impurity removal, which method comprises phases of depositing a first layer on a first wafer surface for providing an active layer, an optional phase of preparation for said first layer for next phase, growing thermal oxide layer on a second wafer, bonding said first and second wafers into a stack, annealing the stack for a crystalline formation in said thermal oxide layer as a second layer, and thinning said first wafer to a pre-determined thickness. The invention concerns also a wafer manufactured according to the method, chip that utilizes such a wafer structure and an electronic device utilizing such a chip.

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