A high performance self modifying on-the-fly alterable logic...

Details A high performance self modifying on-the-fly alterable logic... A high performance self modifying on-the-fly alterable logic...

H - Electricity

03

K

H03K 19/177 (2006.01) G06F 15/78 (2006.01)

Patent

CA 2264060

A technique for configuring arrays of programmable logic cells, including those associated with FPGA devices, through a novel DRAM-based configuration control structure that enables not only "on-the-fly" alterable chip and similar device reconfigurations, but, where desired, self-modifying reconfigurations for differing functionalities of the devices, eliminating current serious reconfigurability limitations and related problems, while providing significantly enhanced system performance at low cost. A large amount of memory is available internal to the FPGA and is accessed with a small number of pins such that the reconfiguration time is, for example, four orders of magnitude faster than the traditional approaches and at notably low cost.

L'invention concerne une technique de configuration de réseaux de cellules logiques programmables, dont celles associées à des circuits FPGA, au moyen d'une nouvelle structure de commande de configuration à mémoire RAM dynamique permettant non seulement des reconfigurations de puces modifiables à la volée et de dispositifs similaires, mais de modifier automatiquement, si besoin est, des reconfigurations pour différentes fonctionnalités des dispositifs, d'éliminer les limitations de reconfigurabilité courantes majeures et les problèmes en découlant, et d'augmenter sensiblement les performances à faible coût. Un volume important de mémoire est disponible à l'intérieur du FPGA et est accessible au moyen d'un petit nombre de broches de sorte que le temps de reconfiguration soit, par exemple, quatre fois inférieur à celui nécessaire dans les techniques classiques, et ce pour un coût sensiblement inférieur.

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