A high tunability cmos delay element

Details A high tunability cmos delay element A high tunability cmos delay element

H - Electricity

03

H

H03H 11/26 (2006.01) H03K 3/0231 (2006.01) H03K 3/03 (2006.01) H03K 5/13 (2006.01)

Patent

CA 2290723

The delay element consists of a differential amplifier (M15, M8, M2, M6, M5) in which the load transistors (M2, M5) are associated to respective gate biasing transistors (M21, M22) connected in a source follower configuration, and to feedback transistors (M3, M4), which implement a negative impedance in parallel to a positive impedance represented by each of the load transistors (M2, M5). The modulation of the delay is achieved by modulating the bias currents of the load transistors (M2, M5), the feedback transistors (M3, M4) and the gate biasing transistors (M21, M22).

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