A linear surface memory to spatial tiling algorithm/mechanism

Details A linear surface memory to spatial tiling algorithm/mechanism A linear surface memory to spatial tiling algorithm/mechanism

G - Physics

06

T

G06T 1/60 (2006.01) G06F 12/00 (2006.01) G06F 12/02 (2006.01) G11C 7/10 (2006.01)

Patent

CA 2267870

A computer graphics system and a method of configuring data in a memory unit of a computer graphics system. Generally, the data is configured such that the number of memory page breaks is reduced when data is accessed from the memory for image computation. For example, when the memory is used to store pixel values, each page of the memory is comprised of pixel values for a rectangular or tile array of pixels. This increases the spatial coherence between the pixel values and the pixels of the polygons that are rasterized when the system renders an image. Preferably, a translation algorithm is provided to allow standard operating systems and software applications to work with the tiled configuration of the pixel values in the memory. This algorithm translates the scalar memory address initially provided by the operating system or the software application, and translates that first scalar memory address to a second scalar memory address that will properly access the value for the pixel conventionally associated with the first scalar memory address.

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