A lithographic process using a nanowire mask, and nanoscale...

Details A lithographic process using a nanowire mask, and nanoscale... A lithographic process using a nanowire mask, and nanoscale...

H - Electricity

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H01L 21/335 (2006.01) H01L 21/336 (2006.01) H01L 29/06 (2006.01) H01L 29/775 (2006.01) H01L 51/00 (2006.01)

Patent

CA 2730162

The disclosure pertains to a method for making a nanoscale field effect transistor structure on a semiconductor substrate (120). The method comprises disposing a mask on a semiconductor upper layer (122) of a multi-layer substrate, and removing areas of the upper layer (122) not covered by the mask in a nanowire lithography process. The mask includes two conductive terminals (132, 134) separated by a distance, and a nanowire (110) in contact with the conductive terminals (132, 134) across the distance. The nanowire lithography may be carried out using a deep-reactive- ion-etching, which results in an integration of the nanowire mask (1 10, 132, 134) and the underlying semiconductor layer (122) to form a nanoscale semiconductor channel for the field effect transistor.

L'invention porte sur un procédé de fabrication d'une structure de transistor à effet de champ nanométrique sur un substrat semi-conducteur (120). Le procédé comprend l'agencement d'un masque sur une couche supérieure semi-conductrice (122) d'un substrat multicouche, et l'élimination de zones de la couche supérieure (122) non couvertes par le masque dans un processus de nanolithographie. Le masque comprend deux bornes conductrices (132, 134) séparées par une certaine distance, et un nanofil (110) en contact avec les bornes conductrices (132, 134) sur toute la distance. La nanolithographie peut être réalisée à l'aide d'une gravure profonde par ions réactifs, ce qui se traduit par une intégration du masque en nanofil (110, 132, 134) et de la couche semi-conductrice sous-jacente (122) pour former un canal semi-conducteur nanométrique pour le transistor à effet de champ.

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