A memory cell for embedded memories

Details A memory cell for embedded memories A memory cell for embedded memories

G - Physics

11

C

G11C 11/40 (2006.01) G11C 11/412 (2006.01) G11C 15/04 (2006.01) H01L 27/11 (2006.01)

Patent

CA 2299991

A memory cell comprising an inverting stage, an access transistor coupled between a data line and an input of the inverting stage, the access transistor being responsive to a control signal for selectively coupling the data line and the inverting stage input, a feedback transistor coupled to the inverting stage input and being responsive to an output of the inverting stage for latching the inverting stage in a first logic state and whereby the cell is maintained in a second logic state by a leakage current flowing through the access transistor which is greater than a current flowing through the feedback transistor.

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