A memory device having a power supply-independent low power...

Details A memory device having a power supply-independent low power... A memory device having a power supply-independent low power...

G - Physics

11

C

G11C 8/00 (2006.01) G11C 11/40 (2006.01) G11C 14/00 (2006.01) G11C 16/00 (2006.01) G11C 16/24 (2006.01)

Patent

CA 2258957

The present invention relates to a bit line clamping scheme for non-volatile memories (10). The bit line (35) voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.

Cette invention a trait à un alignement de ligne binaire pour mémoires permanentes (10). La tension de la ligne binaire (35) est maintenue à un seuil désiré de manière à éviter des effets de trouble de lecture, tout en restant indépendante des écarts d'alimentation électrique et ne consommant pour ainsi dire pas d'énergie. Elle porte sur des dispositifs à mémoire pratiques conçues pour fonctionner à la fois à haute (5 volts) et à basse tension (3,3 et 2,5 volts).

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