A method and arrangement for avoiding erroneous...

H - Electricity – 04 – B

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H04B 3/23 (2006.01) H03M 1/06 (2006.01)

Patent

CA 2030623

A method and arrangement for avoiding erroneous echo-elimination and/or equalization resulting from non-linearities of a D/A- converter (12) and/or an A/D-converter (15) in a telecommunication system, an error signal (e n) being formed for updating a filter (16) for adaptive echo-elimination and/or a filter (18) for adaptive equalization. In accordance with the invention, the error signal (e n) is also used to adjust the values of given devices (C41 - C43, C1 - C1), e.g. capacitors, in the converters (12, 15) for avoiding non-linearities in the converters. The signals are therewith formed from the error signal for the purpose of adjus- ting the converters in accordance with appropriate algorithms in separate logic devices (21, 22).

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