G - Physics – 06 – F
Patent
G - Physics
06
F
354/223
G06F 11/08 (2006.01) G06F 11/10 (2006.01)
Patent
CA 1207914
ERROR CORRECTION SYSTEM Abstract of the Disclosure A method and apparatus for correcting single bit errors in a data word stored in a first memory device without requiring the data word to include an error correction code includes a multi-stage dynamic shift register for dividing a data word by a polynomial during the time the data word is being written into the first memory device resulting in the generation of a remainder which is stored in a second memory device. When reading the data word from the first memory device, the data word is again divided by the same polynomial. The remainder generated by the second division is com- pared with the remainder stored in the second memory device. If the remainders do not match, indicating an error was introduced into the data word during storage or retrieval of the data word in the first memory de- vice, the remainder stored in the second memory device is shifted into the dynamic shift register and followed by the shifting of a number of zero bits into the shift register which is equal to the maximum number of bits in the data word located in the second memory device. As each zero bit is shifted into the shift register, a bit counter is incremented and the output bit of each stage of the shift register is examined. When the output of all the stages in the shift register except the last stage is zero and the last stage contains a binary bit one, the count of the bit counter points to the bit location in the data word stored in the second memory device locating the bit that is in error. The binary bit at this bit location is then complemented, thereby correcting the error bit in the data word.
440814
Ncr Corporation
Smart & Biggar
LandOfFree
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