A method of and apparatus for implementing a reconfigurable...

Details A method of and apparatus for implementing a reconfigurable... A method of and apparatus for implementing a reconfigurable...

H - Electricity

03

M

H03M 13/00 (2006.01)

Patent

CA 2567248

A chip architectural core is described for use in decoding one or more vectors received by the core in accordance with one or more recursive and/or non- recursive systematic trellis codes of varying sizes and constraints K, as well as generator polynomials. The core comprises: a decoder including (a) a reconfigurable network of ACS blocks (114), BMU generators (110) and trace- back mechanisms (116) for both recursive and non-recursive systematic forms, and (b) reconfigurable connections between the ACS blocks, BMU generators and trace-~back mechanisms, arranged so that the precise number of network components can be continuously rearranged and interconnected in a network as a function of size and the constraint K and generator polynomial of each code used for encoding the vectors received by the core.

L'invention concerne un coeur architectural de microcircuit intégré permettant le décodage d'un ou de plusieurs vecteurs reçus par le coeur conformément à un ou plusieurs codes en treillis systématiques récursifs et/ou non-récursifs, présentant diverses dimensions et contraintes K, et divers polynômes générateurs. Le coeur contient: un décodeur comprenant (a) un réseau reconfigurable de blocs ACS (114), des générateurs BMU (110), et de mécanismes de retraçage (116) pour les formes systématiques récursives et non récursives, et (b) des connections reconfigurables entre les blocs ACS, les générateurs BMU et les mécanismes de retraçage, conçus de manière à permettre le réarrangement et l'interconnexion continuels en réseau du nombre précis de composants du réseau en fonction de la dimension et de la contrainte K, et du polynôme générateur de chaque code utilisé pour le codage des vecteurs reçus par le coeur.

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