G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 1/32 (2006.01)
Patent
CA 2704742
A multi-core processor and a frequency conversion device thereof as well as a method of communication between the cores are disclosed. Each processor core of the multi-core processor includes a frequency conversion device, which includes a multi-bit state changing means, a multiple selector, a frequency conversion coefficient register, a multi-input OR gate and a clock-gating circuit unit. A common original clock is sent to the frequency conversion device of each processor core at work. The frequency conversion device real-timely reads the value of the frequency conversion coefficient register of a corresponding processor core and receives data transmission valid signals from other processor cores. By gating the common original clock, a frequency conversion function of the processor core is completed. In the invention, the dynamic frequency conversion function of a multi-core processor is achieved, the frequency conversion coefficient control may be performed by each processor core independently, and a highly effective synchronous communication may be maintained between the processor cores, so as to reduce the overall running consumption of the processor and save power on different processor cores of the multi-core processor or on different IP modules in SOC.
L'invention concerne un processeur multicoeur et un convertisseur de fréquence associé, ainsi qu'un procédé permettant de communiquer des données entre les coeurs. Chaque coeur du processeur multicoeur comprend un convertisseur de fréquence (1). Ce convertisseur comprend un convertisseur d'état multibit (11), un sélecteur multiplex (12), un système d'enregistrement de coefficient de conversion de fréquence (13), une porte "OU" multi-entrée (14) et une unité de circuit de déclenchement d'horloge (15). L'horloge commune d'origine est envoyée au convertisseur de fréquence de chaque coeur de processeur. Le convertisseur de fréquence lit en temps réel la valeur du système d'enregistrement de coefficient de conversion de fréquence (13), et reçoit des valeurs valides de signaux qui sont envoyés au coeur de processeur à partir d'autres coeurs de processeur. Le déclenchement de l'horloge commune d'origine permet de mettre un terme à une fonction de conversion de fréquence du coeur de processeur.
Hu Weiwu
Zhang Ge
Cassan Maclean
Institute Of Computing Technology Of The Chinese Academy Of Scie
LandOfFree
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