A multi-processor computer system

G - Physics – 06 – F

Patent

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Details

G06F 15/16 (2006.01) G06F 13/16 (2006.01) G06F 13/40 (2006.01) G06F 15/17 (2006.01) G06F 15/80 (2006.01)

Patent

CA 2313810

A multi-processor computer system comprising one or more computer modules connected to a host computer via a common PCI bus system backplane, the host computer comprising a host microprocessor and associated memory unit, and the or each computer module comprising a PCI connector connected to the PCI backplane; at least one CPU; a PCI backplane interface installed between the PCI connector and the or each CPU for forwarding PCI memory cycles to and from the PCI backplane; and memory address translating means for translating memory cycles forwarded from the PCI backplane; wherein the or each CPU comprises; a local microprocessor having an associated local memory unit installed on a local memory bus; a bridge installed between the local memory bus and the PCI interface of the respective computer module; wherein said CPU bridge includes an address decoder which is programmed to a local address range for access to the respective computer module address space including the local memory unit associated with the or each CPU of that module; wherein said PCI interface is programmed to forward PCI memory cycles from the PCI backplane which fall within an address range which is different from the local address range of the or each CPU of that module and which is different for each computer module in the system; and wherein said translating means operates to translate memory cycles falling within said address window into corresponding addresses of the local address space of the respective computer module such that addresses corresponding to a local memory unit of that module may be decoded by the respective CPU bridge decoder; whereby each microprocessor of the system can access the entire PCI memoryspace comprising the memory space of earh computer module including the local memory units of all microprocessors of the system.

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