A novel massively parrallel supercomputer

G - Physics – 06 – F

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G06F 15/16 (2006.01) G06F 12/08 (2006.01) G06F 15/00 (2006.01) H05K 7/20 (2006.01)

Patent

CA 2437039

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes (20) are interconnected by multiple independent networks (26) that optimally maximizes packet communications throughput and minimizes latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance.

L'invention concerne un nouveau superordinateur massivement parallèle de l'ordre de centaines de téraflop comprenant des architectures nodales basées sur la technologie du système sur puce. Chaque noeud de traitement comporte un circuit intégré spécifique (ASIC), dont les noeuds sont reliés par plusieurs réseaux (26) indépendants qui maximisent de façon optimale le débit de traitement de communications par paquets et minimisent les temps d'attente. Les nombreux réseaux peuvent comporter trois réseaux à grande vitesse pour le passage de message algorithmique parallèle comprenant un tore, une arborescence globale et un réseau asynchrone global fournissant des fonctions de barrière globale et de notification. Ces nombreux réseaux indépendants peuvent être utilisés en collaboration ou de manière indépendante en fonction des besoins ou des phases d'un algorithme pour optimiser la performance du traitement algorithmique.

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