A phase detector

Details A phase detector A phase detector

G - Physics

01

R

G01R 25/00 (2006.01) G11B 20/10 (2006.01) G11B 20/14 (2006.01) H03L 7/091 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2258656

A phase detector determines a phase error value dependent on the relative phase between a local oscillator signal, used for the system clock, and an input signal received over a PR (a, b, b, a) channel. The error value is used to lock the phase and frequency of an input signal to the phase and frequency of the clock in a phase-lock loop (Figure 1, not shown). The input signal is sampled at regular intervals in accordance with the local oscillator signal, and the sampled values provided on a line 10. A threshold dicer 22 selects an ideal sample value for a sampling point by comparing the sampled values with thresholds received on threshold inputs 23 to 26. A subtracter 32 determines a difference value which corresponds to a difference between the ideal sample value and the actual sample value for that sampling point. A subtracter 28 and a delay register 29 operate to determine the sense of change to the ideal sample value from a ideal sample value for a preceding sampling point. A second subtracter 42 and a second delay register 31 determine the sense of change to the ideal sample value for a preceding sampling point from a ideal sample value for a twice preceding sampling point. The phase error value provided is dependent on the senses of change detected and on the difference value.

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