A process for forming a semiconductor structure

H - Electricity – 01 – L

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H01L 21/20 (2006.01) C30B 25/18 (2006.01) H01L 21/36 (2006.01) H01L 21/8252 (2006.01) H01L 21/8258 (2006.01) H01L 27/06 (2006.01) H01L 27/15 (2006.01) H01S 5/02 (2006.01) H01S 5/026 (2006.01) H01L 21/316 (2006.01) H01L 33/00 (2006.01)

Patent

CA 2399394

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer (24) on a silicon wafer (22). The accommodating buffer layer (24) is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer is preferably formed by oxygen diffusion through the oxide buffer and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The process further may comprise formation of template layers (28, 30) and a semiconducteur buffer layer (32). It's especially suited for cointegration of compound semiconducteur and Si SMOS devices.

L'invention concerne des couches épitaxiales de haute qualité faites de matériaux semi-conducteurs composés, destinées à recouvrir des plaquettes de grande dimension et pouvant être obtenues en fabriquant en premier lieu une couche tampon (24) d'adaptation sur une plaquette (22). La couche tampon d'adaptation est une couche d'oxyde monocristallin séparée de la plaquette par une couche d'interface amorphe (28) d'oxyde de silicium. La couche d'interface amorphe élimine les déformations et permet de générer une couche tampon d'adaptation d'oxyde monocristallin de qualité. La couche tampon d'adaptation est connectée en réseau avec la couche inférieure de silicium et la couche supérieure (26) à semi-conducteurs composés monocristallins. Tout défaut de réseau entre la couche tampon d'adaptation et le substrat de silicium sous-jacent est pris en charge par la couche d'interface amorphe.

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