G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 17/50 (2006.01) G06F 19/00 (2006.01)
Patent
CA 2359048
A regionally time multiplexed emulation system includes an emulator for emulating a circuit design. The emulator includes a plurality of reconfigurable logic devices with buffered I/O pins and reconfigurable logic elements. The reconfigurable logic devices are reconfigurable to emulate a circuit design using at least one user clock to clock the logic elements and at least one signal routing clock to time multiplex the routing of emulation signals between the reconfigurable logic devices, with the at least one signal routing clock being independent of the at least one user clock.
Un système d'émulation multiplexé temporellement par région comporte un émulateur pour émuler une conception de circuit. L'émulateur comprend plusieurs dispositifs logiques reconfigurables dotés de broches entrée/sortie tamponnées et d'éléments logiques reconfigurables. Les dispositifs logiques reconfigurables sont reconfigurables pour l'émulation d'une conception de circuit, au moyen d'au moins une horloge utilisateur synchronisant les éléments logiques et d'au moins une horloge d'acheminement de signal assurant le multiplexage temporel de l'acheminement des signaux d'émulation entre les dispositifs logiques reconfigurables, au moins l'horloge d'acheminement de signaux étant indépendantde de la ou desdites horloges utilisateur.
Barbier Jean
Lepape Olivier
Reblewski Frederic
Mentor Graphics Corporation
Riches Mckenzie & Herbert Llp
LandOfFree
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