G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 12/00 (2006.01) G06F 12/02 (2006.01) G06F 13/16 (2006.01) G09G 5/39 (2006.01) G09G 5/399 (2006.01) G06F 12/10 (2006.01)
Patent
CA 2313257
An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers 154 having an accelerated graphics port (AGP) includes a set of registers 165, 166 defining a range of addresses handled by the memory controller 154 that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) 156 for mapping memory. The GART 156 includes page table entries 208 having translation information to remap virtual addresses 200 falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers 154, 190 have an AGP, wherein each of the plurality of the memory controllers 154, 190 supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used far AGP transactions.
Fetherstonhaugh & Co.
Micron Technology Inc.
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