Access verification arrangement for digital data processing...

Details Access verification arrangement for digital data processing... Access verification arrangement for digital data processing...

G - Physics

06

F

354/243

G06F 12/14 (2006.01)

Patent

CA 1237200

Abstract of the Disclosure A bus interface unit for connecting a processor to a memory to form a digital data processing system. The storage locations in the memory are grouped in pages each having a selected access rights mode which regulate access to the data stored therein by the programs, each of which has a selected access rights mode. The access rights are assigned on a page by page basis. If an access request from a program requires transfers to multiple locations, the p;rocessor will normally perform an access verification on the first location while it is in the first transfer operation, and then perform the transfer operation and successive transfer operations. If the transfer operations require accesses to separate pages in memory, a microtrap operation is performed and the processor performs access verifications on locations in both pages before performing any transfers.

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