Active dynamic memory cell

Details Active dynamic memory cell Active dynamic memory cell

G - Physics

11

C

352/82

G11C 11/401 (2006.01) G11C 11/24 (2006.01) G11C 11/404 (2006.01) H01L 27/108 (2006.01)

Patent

CA 1322250

AN ACTIVE DYNAMIC MEMORY CELL Abstract A dynamic memory cell comprises a storage transistor and an access transistor. The gate of the storage transistor is utilized as a storage capacitor electrode, and is connected to its source by a high resistance resistor. The drain of the storage transistor is connected to a source of electrical potential (e.g., Vcc). The access transistor connects the source of the storage transistor to a bit line. This arrangement multiplies the effective capacitance of tile gate storage capacitor, reducing the area required and hence making the structure more compact than a typical inactive (one transistor) DRAM cell. In a preferred embodiment, the resistor is formed to overlie the storage transistor, and the drain of the storage transistor is connected to Vcc by means of the sidewall of a trench formed in the semiconductor substrate.

574312

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