Active load network

Details Active load network Active load network

G - Physics

01

R

324/58.1, 324/58

G01R 31/28 (2006.01) G01R 19/165 (2006.01) G01R 31/319 (2006.01)

Patent

CA 1273061

ACTIVE LOAD NETWORK ABSTRACT An active load network for a device under test includes a logic circuit for anticipating the out- put state of the device under test and for turning on either a current source of a current sink to properly load its output. The current sink and current source each comprise a pair of CMOS transistors connected in series. One of each transistor pair turns on to either source or sink current and the other provides a variable impedance controlled by the voltage at its gate to regulate the amount of current. A pull-to- center transmission gate is also provided which pulls the output of the device under test to a level between a logic high and logic low when it is turned off.

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