G - Physics – 11 – C
Patent
G - Physics
11
C
352/82.3
G11C 11/34 (2006.01) G11C 11/406 (2006.01) H03K 19/017 (2006.01)
Patent
CA 1143478
ABSTRACT Circuitry for automatically and selectively refreshing a dynamic node to a desired logic level. Nodes at ground potential are left at ground while nodes at all intermediate level are brought up to a supply voltage level. In a preferred use the dynamic node is a digit line in a random access memory. The circuitry includes a first transistor connected between the drain supply and a digit line having a gate connected to the source of a second transistor. The drain of the second transistor is connected to a clocked source of potential at least one threshold above the drain supply. The gate of the second transistor isprecharged to a potential near the drain supply voltage preferrably concurrent with precharging of digit lines in the memory proper. A third transistor is connected between the gate of the second transistor and the digit line and has agate connected to a clocked source of a reference potential between a digit lineprecharge level and the level of one threshold above ground. After the state of a memory cell is read out by a sense amplifier, the reference potential is applied to the gate of the third transistor to discharge the gate of the second transistor in the event that the digit line is at a low voltage. If the cell read out on the digit line was at n high potential the gate of tile second transistorremains charged so that when a potential exceeding the drain voltage by at least one threshold is applied to the drain of the second transistor it is coupled through to the gate of the first transistor which in turn pulls the digit line potential to the drain supply voltage.
370519
Kirby Eades Gale Baker
Mostek Corporation
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