Adder cell for "carry-save" arithmetic

Details Adder cell for "carry-save" arithmetic Adder cell for "carry-save" arithmetic

G - Physics

06

F

354/204

G06F 7/50 (2006.01)

Patent

CA 1312384

ABSTRACT OF THE DISCLOSURE An adder cell in which the sum signal and the carry signal are formed with equal speed is provided for employment in "carry-save" adders, wherein the sum signal and the carry signal are separately forwarded to separate inputs of following adder cells. The circuit of the adder cell is designed such that the sum signal as well as the carry signal each have to traverse only two gates, so that the running times of sum signal and carry signal are approximately identical and shorter than the maximum running time of conventional adder cells.

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