Address computation system for digital processing apparatus

Details Address computation system for digital processing apparatus Address computation system for digital processing apparatus

G - Physics

06

F

354/230.73

G06F 9/32 (2006.01) G06F 9/345 (2006.01)

Patent

CA 1223664

-15- ADDRESS COMPUTATION SYSTEM FOR DIGITAL PROCESSING APPARATUS ABSTRACT An address computation system for updating starting addresses of data arrays in an array processor within an instruction cycle. A first set of registers is provided for storing starting addresses for each array. A second set of registers is provided for storing current addresses for each array. Logic is provided for initially providing, at the beginning of a series of computation steps to be executed repetiti- vely, an address from a register in the first set of registers, changing that address, and storing it back in the same register and in a corresponding register in the second set, thereby updating the starting address for the next repetition of those computational steps while advancing the current address to the second of those steps.

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