Address generator with variable scan patterns

Details Address generator with variable scan patterns Address generator with variable scan patterns

G - Physics

06

F

354/239, 354/230

G06F 12/02 (2006.01) G06F 9/35 (2006.01) G06T 1/60 (2006.01)

Patent

CA 1315005

Abstract An apparatus for reading a first addressable memory and writing into a second addressable memory wherein the first addressable memory is logically arranged in a rectangular matrix and is scanned at an arbitrary angle with respect to the matrix for producing a plurality of scan patterns whose parameters can be altered and controlled by an external source, while the second addressable memory, also arranged in a rectangular matrix, is written into along parallel rows and columns. The apparatus is particularly adapted for use with a digital map display system having an airborne computer for generating the scan parameters.

601869

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