Address multiplexing in pseudo-dual port memory

Details Address multiplexing in pseudo-dual port memory Address multiplexing in pseudo-dual port memory

G - Physics

11

C

G11C 7/22 (2006.01) G11C 8/16 (2006.01)

Patent

CA 2717842

A pseudo-dual port memory address multiplexing system includes a control circuit (103) operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit (105) monitors a read operation and generates a switching signal (WCLK) when the read operation is determined to be complete. A multiplexer (104) is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time.

La présente invention concerne un système de multiplexage dadresses à port pseudo-double comportant un circuit de commande (103) servant à identifier une requête de lecture et une requête décriture à réaliser au cours dun unique cycle dhorloge. Un circuit de suivi temporel autonome (105) surveille une opération de lecture et génère un signal de commutation (WCLK) lorsquil est déterminé que lopération de lecture est complétée. Un multiplexeur (104) est sensible au signal de commutation pour la fourniture sélective dune adresse de lecture et une adresse décriture à lunité de mémoire dadresses à linstant approprié.

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