Address transform method and apparatus for transferring...

Details Address transform method and apparatus for transferring... Address transform method and apparatus for transferring...

G - Physics

06

F

354/225

G06F 12/02 (2006.01) G06F 11/00 (2006.01)

Patent

CA 1299293

ABSTRACT OF THE DISCLOSURE An address path which transfers addresses from a number of sources includes an incrementing circuit. The address includes a plurality of address bits and integrity bits. The address bits are applied to the incrementing circuit while the integrity bits are applied in parallel to a programmable logic device (PLD). While the address is being transferred or incremented as required, the PLD independently generates a number of transform bits defining a characteristic of the number of address bits predicted to change state. Thereafter, the transform bits are used to transform the address integrity bits for transfer with the incremented address. The incremented address, transform bits and integrity bits are logically combined for verifying that the address was transferred and/or incremented without error.

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