Address translation control system

G - Physics – 06 – F

Patent

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354/239

G06F 12/10 (2006.01)

Patent

CA 1226372

ADDRESS TRANSLATION CONTROL SYSTEM ABSTRACT OF THE DISCLOSURE Disclosed is an address translation control system comprising an address translation buffer having a plurality of entries each including at least a valid flag, a logical address field, and a physical address field, a memory array having copies of at least the valid flag and the physical address field, and a purge register for storing information showing a portion of the contents of the address translation buffer to partially purge the address translation buffer. When the coincidence between the physical address of the address translation buffer and the contents of the purge register does not occur, the ordinary access processing can be carried out, and when the entry of the memory array is accessed in turn and the coincidence between the physical address in the memory array and the contents of the purge register occurs, the partial purge is performed by clearing the valid flags of the corre- sponding entries of the address translation buffer and the memory array. Thus, the partial purge processing can be carried out separately from the ordinary access processing, and the application efficiency for the address translation buffer increases. Particularly, the performance efficiency for the application of this invention to a pipeline system or a virtual machine can be increased.

469913

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