Addressing for large dynamic ram

Details Addressing for large dynamic ram Addressing for large dynamic ram

G - Physics

11

C

352/82.4

G11C 13/00 (2006.01) G11C 8/04 (2006.01) G11C 11/408 (2006.01)

Patent

CA 1314990

ABSTRACT A DRAM semiconductor memory chip comprised of a matrix of rows and columns having a bit storage cell at each location, means for receiving row and column address bits in multiplexed form on a single address bus, the multiplexing arrangement being such that the number of column address bits exceeds the number of row address bits, whereby a system using the DRAM memory chip has access to an enlarged page size.

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