Addressing technique for a device controller's memory

Details Addressing technique for a device controller's memory Addressing technique for a device controller's memory

G - Physics

06

F

354/233, 340/85

G06F 13/00 (2006.01) G06F 13/12 (2006.01)

Patent

CA 1081858

ABSTRACT A memory in a device controller divided into sections, equal in number to the potential number of devices controllable by the controller, each section having a plurality of storage locations for storing the same topology of information in like positioned locations in the other sections is provided. Apparatus for addressing the locations independent of the addressing of the sections is provided, the sections being addressable independent of the active device or under normal conditions in direct relationship to the identity of the active device. -1-

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