All digital phase-frequency locked loop

Details All digital phase-frequency locked loop All digital phase-frequency locked loop

H - Electricity

03

L

328/28

H03L 7/08 (2006.01) H03L 7/099 (2006.01)

Patent

CA 1161910

AN ALL DIGITAL PHASE-FREQUENCY LOCKED LOOP ABSTRACT OF THE DISCLOSURE An all digital phase-frequency locked loop consists of an up-down counter as a phase-frequency comparator and low pass filter, a frequency multiplier as a controlled oscillator and a dividing counter as a jitter averaging filter. A reference signal is applied to the up-count input of the up-down counter and the feedback signal is applied to the down-count input of the up-down counter. The up-down counter's output controls the frequency rate multiplier to generate a variable frequency output. This variable frequency is further filtered by a counter to average the jitter and increase the signal to noise ratio before it is applied to the down-count input of the counter. The loop has a wide pull-in range, a fast acquisition time and is highly suitable for integration because of its all digital nature.

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