All-digital quadrature modulator

Details All-digital quadrature modulator All-digital quadrature modulator

H - Electricity

04

B

332/32, 325/64

H04B 1/04 (2006.01) H04L 27/12 (2006.01) H04L 27/20 (2006.01)

Patent

CA 2003938

Abstract of the Disclosure A CPFSK quadrature modulator (300) is disclosed utilizing an all-digital implementation. The serial data input signal (201) is formatted into parallel overlapping bits using a shift register (202), an up/down counter (206), and an interpolation counter (204), and applied as address lines to in-phase and quadrature-phase memories (208, 210). A multiple of the bit clock is used to address carrier generation ROMs (216, 218). The carrier signal is then modulated by the in-phase and quadrature-phase data signals (212, 214, 222), converted to an analog signal by a D/A converter (250), and low pass filtered (254) to generate the analog output signal (255). A single ROM (440) is utilized to implement all the look-up tables, multipliers, and adder. The all-digital implementation allows for precise control of the modulation index to h=0.5 ? 0.05 percent over time, temperature, power levels, etc.

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