Amethyst controller watch dog timer

G - Physics – 06 – F

Patent

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354/222, 314/7

G06F 11/00 (2006.01) G06F 13/28 (2006.01)

Patent

CA 1096506

AMETHYST CONTROLLER WATCH DOG TIMER ABSTRACT OF THE DISCLOSURE In a controller for directing a host machine in- cluding a central processor for program execution, a system bus controlled by the central processor for carrying data, address, and control signals, a data memory coupled to the system bus, and a direct memory access module for convey- ance through the system bus of a hold signal to the central processor upon receipt of an enabling signal, and upon ac- knowledgement for control assumptions of the system bus for generating address and state signals that will directly access the data memory for host machine update. In addition, a fault timer is included comprising a counter clocked at a given frequency for reset by the state signal from the dir- ect memory access module if within a given period, and upon reset absence thereafter for generating a fault signal, and a bistable unit operative to receive the fault signal from said counter for clocked latching thereof, and for generating a hold signal through the direct memory access module to the central processor and a disabling signal to the host machine. -1-

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