Amplifier arrangement

H - Electricity – 03 – F

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330/35

H03F 1/02 (2006.01) H03F 1/34 (2006.01) H03F 3/45 (2006.01)

Patent

CA 1229138

14 ABSTRACT: Amplifier arrangement. A bias current (It) which is dependent on the input signal (Vi) is applied to the junction point (2) of the source electrodes of a first and a second transis- tor (T1, T2). The amplifier comprises a control circuit, which ensures that this bias current (It) cannot increase more than is necessary to obtain a high slew rate, thereby minimizing dissipation by the arrangement. This control circuit comprises a third and a fourth transistor (T3, T4) which are arranged in parallel with the first transistor (T1) and the second transistor (T2), respectively, and which carry currents (I3, I4) which are proportional to the currents (I1, I2) in the first and the second transis- tor (T1, T2). A selection circuit (5) applies the smaller of the two currents (I3, I4) in the third and the fourth transistor (T3, T4) to an output (8), where this current is compared with a reference current (I0) from a current source (9). The difference between these currents is applied to a current amplifier (10), which supplies an in- creasing bias current (It) until the smaller of the two currents (I3, I4) in the third and the fourth transistor (T3, T4) has become equal to the reference current (I0).

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