Amplifier with reduced input capacitance

Details Amplifier with reduced input capacitance Amplifier with reduced input capacitance

H - Electricity

03

F

H03F 3/185 (2006.01) H03F 1/14 (2006.01) H03F 1/56 (2006.01) H03F 3/50 (2006.01)

Patent

CA 2236241

A JFET preamplifier for use with a high impedance transducer, having an inherently capacitive input bias impedance. The capacitance of the input bias impedance is effectively neutralized by capacitively coupling the JFET gate bias circuit to the source electrode of the JFET. The JFET preamplifier is configured as a source follower which reduces any capacitance between the JFET gate and source electrode by the open loop gain of the amplifier. By capacitively coupling the JFET gate bias circuit capacitance to the JFET source electrode, the overall input capacitance of the preamplifier stage is reduced.

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