An amps receiver system using a zero-if architecture

H - Electricity – 04 – W

Patent

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Details

H04W 88/06 (2009.01) H03G 3/30 (2006.01) H04B 1/30 (2006.01)

Patent

CA 2474350

An AMPS receiver system utilizing a ZIF architecture and processing received forward link signals in the digital domain. The AMPS receiver system includes an antenna (105), a direct converter (110), high dynamic A/D converters (120, 130), low pass filters (140, 150), a phase shifter (160), a digital FM demodulator (180), an accumulator (185) and a controller (190). The direct converter (110) further includes a low noise amplifier (112), a splitter (113), mixers (114, 116) and low pass filters (118, 119). The controller (190) adjusts the gains of the low noise amplifier (112) and the digital VGA (170) based on the average power of the signal outputted by the digital VGA (170).

L'invention concerne un système récepteur AMPS faisant appel à une architecture sans fréquence intermédiaire et traitant les signaux de liaison aval reçus dans le domaine numérique. Ledit système récepteur AMPS comprend une antenne (105), un convertisseur direct (110), un convertisseur analogique-numérique (120, 130) à dynamique élevée, des filtres passe-bas (140, 150), un déphaseur (160), un VGA numérique (170), un démodulateur FM numérique (180), un accumulateur (185) et un dispositif de commande (190). Le convertisseur direct (110) comprend en outre un amplificateur à faible bruit (112), un diviseur (113), des mélangeurs (114, 116) et des filtres passe-bas (118, 119). Le dispositif de commande (190) ajuste les gains de l'amplificateur à faible bruit (112) et du VGA numérique (170) en fonction de la puissance moyenne du signal émis par le VGA numérique (170).

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