An exciter circuit for digital television transmitters

Details An exciter circuit for digital television transmitters An exciter circuit for digital television transmitters

H - Electricity

04

N

H04N 5/38 (2006.01) H01Q 5/00 (2006.01) H01Q 21/26 (2006.01) H03L 7/185 (2006.01) H03M 13/15 (2006.01) H03M 13/25 (2006.01) H03M 13/27 (2006.01) H03M 13/29 (2006.01) H04J 3/06 (2006.01) H04L 1/00 (2006.01) H04L 27/00 (2006.01) H04L 27/34 (2006.01) H04L 27/36 (2006.01) H04N 5/04 (2006.01) H04N 5/067 (2006.01) H04N 5/21 (2006.01) H04N 7/08 (2006.01) H04N 7/66 (2006.01) H04N 11/24 (2006.01) H04N 1/00 (2006.01) H04N 11/00 (2006.01) H04N 5/44 (2006.01) H04N 7/24 (2006.01) H04N 7/62 (2006.01)

Patent

CA 2233245

An excites circuit for receiving input television digital signals from a source and converting the television digital signals into a standard format for broadcasting by television transmitter power amplification stages via an antenna, comprises a data recovery circuit for extracting data and clock signals from the input television digital signal for outputting the extracted the digital clock signals for separately outputting the digital clock signals and the digital data signals, a randomiser circuit for altering the order of the extracted digital data signals in accordance with digital television standards, an encoder circuit for encoding the digital data signals into packets synchronised to receive the digital data signals at the input television digital signal rate, an interleaves circuit for performing a convolutional interleaving of the packets of digital data signals synchronised to receive packets of digital data signals at a second layer rate, an encoder circuit for encoding the convoluted interleaved digital data signals with a trellis code according to digital television standards, a sync insertion circuit for inserting segment and field sync signal into the encoded digital data signals, a filter circuit for limiting the spectrum of the encoded digital data signals to the digital television standard, a signal insertion circuit for inserting the extracted digital clock signal into the output of the filter circuit, a digital to analogue conversion circuit for converting the digital data signals and the digital clock signals into analogue signals in form for transmission by the power amplifier stage, and a rate controler for receiving input signals and controlling output signals even in absence of the input signal.

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