G - Physics – 11 – C
Patent
G - Physics
11
C
G11C 15/04 (2006.01) G11C 11/412 (2006.01) H01L 21/8244 (2006.01) H01L 27/11 (2006.01)
Patent
CA 2401025
A memory cell comprising an inverting stage, an access transistor coupled between a data line and an input of the inverting stage, the access transistor being responsive to a control signal for selectively coupling the data line and the inverting stage input, a feedback transistor coupled to the inverting stage input and being responsive to an output of the inverting stage for latching the inerting stage in a first logic state and whereby the cell is maintained in a second logic state by a leakage current flowing through the access transistor which is greater than a current flowing through the feedback transistor.
L'invention porte sur une cellule mémoire comportant: un étage d'inversion; un transistor d'accès monté entre une ligne de données et une entrée de l'étage d'inversion, ledit transistor réagissant à un signal de commande reliant sélectivement la ligne de données à l'entrée de l'étage d'inversion; un transistor d'asservissement relié à l'entrée de l'étage d'inversion réagissant à un signal de sortie de l'étage d'inversion et verrouillant l'étage d'inversion dans un premier état logique, la cellule étant maintenue dans un deuxième état logique par un courant de fuite traversant le transistor d'accès, plus intense que celui traversant le transistor d'asservissement.
Foss Richard C.
O'connell Cormac M.
Mosaid Technologies Incorporated
Ogilvy Renault
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