An interleaving scheme for blocks in a packet switched system

Details An interleaving scheme for blocks in a packet switched system An interleaving scheme for blocks in a packet switched system

H - Electricity

04

L

H04L 1/18 (2006.01) H03M 13/27 (2006.01) H04B 1/00 (2006.01) H04L 1/00 (2006.01)

Patent

CA 2325993

The present invention discloses a method and system for interleaving blocks of a packet to minimize the effects of burst errors and at the same time enhance the effectiveness of the ARQ protocol. A packet is first divided into a plurality of blocks. Each block is then individually encoded and inner-block interleaved. Thereafter the blocks are interleaved over a longer time period. By performing two stages of interleaving, the present invention allows for the size of a packet block to be kept at a minimum, which increases the effectiveness of the ARQ protocol, and provides greater interleaving of the packet's data elements so as to minimize the effects of burst errors.

La présente invention concerne un procédé et un système d'entrelacement de blocs d'un paquet qui permet de réduire au minimum les effets dus à des paquets d'erreurs, et en même temps d'améliorer l'efficacité du protocole ARQ. Un paquet est d'abord divisé en plusieurs blocs. Chaque bloc est ensuite codé individuellement et entrelacé de façon interne. Après quoi les blocs sont entrelacés sur une plus longue période temporelle. Par la mise en oeuvre de deux étapes d'entrelacement, la présente invention permet de maintenir au minimum la taille d'un bloc de paquets, ce qui accroît l'efficacité du protocole ARQ et permet d'obtenir un plus grand entrelacement des éléments de données de paquet de façon à réduire au minimum les effets dus à des paquets d'erreurs.

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