Analog memory and image processing system

Details Analog memory and image processing system Analog memory and image processing system

G - Physics

11

C

G11C 27/02 (2006.01) G11C 27/00 (2006.01) G11C 27/04 (2006.01) H04N 9/28 (2006.01)

Patent

CA 2304788

The fixed pattern noise of an analog memory is reduced. The transmission paths of an address selection signal (SL) between an address generating unit (10) and memory devices (21) are so constructed so that the electrical characteristics when the address selection signal (SL) drives the memory devices (21) are nearly uniform to an extent that fixed pattern noise is not included in the output signal of the analog memory. A buffer unit (50) which stores the address selection signal temporarily and outputs it is provided between the address generating unit (10) and the memory devices (21) and the output characteristics of the buffer unit (50) are uniform for the memory devices (21). Further, the wiring between the buffer unit (50) and the memory devices (21) are so constructed that the electrical characteristics of the wiring are nearly uniform. With this construction, the charge feed-through noise of the memory devices (21) can be nearly uniform, and the fixed pattern noise can be suppressed.

Selon cette invention, on réduit le bruit de structure fixe d'une mémoire analogique. Les voies de transmission d'un signal (SL) de sélection d'adresse entre un générateur (10) d'adresses et des mémoires (21) sont conçues de sorte que les caractéristiques électriques, lorsque le signal (SL) de sélection d'adresse commande les mémoires (21), soient quasiment uniformes au point que le bruit de structure fixe ne soit pas inclus dans le signal de sortie de la mémoire analogique. Une unité tampon (50), enregistrant provisoirement et émettant le signal de sélection d'adresse, est ménagée entre le générateur (10) d'adresses et les mémoires (21), les caractéristiques de sortie de l'unité tampon (50) étant uniformes pour les mémoires (21). De plus, le câblage entre l'unité tampon (50) et les mémoires (21) est conçu de sorte que ses caractéristiques électriques soient à peu près uniformes. Avec cette structure, le bruit de la traversée de la charge des mémoires (21) peut être à peu près uniforme, et le bruit de structure fixe supprimé.

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