Annealing method for iii-v deposition

Details Annealing method for iii-v deposition Annealing method for iii-v deposition

H - Electricity

01

L

148/2.4, 148/3.7

H01L 29/12 (2006.01) H01L 21/20 (2006.01) H01L 21/205 (2006.01) H01L 29/06 (2006.01)

Patent

CA 1320103

ANNEALING METHOD FOR III-V DEPOSITION Abstract of the Disclosure A method for producing wafers having deposited layers of III-V materials on Si or Ge/Si substrates is disclosed. The method involves the use of multiple in situ and ex situ annealing steps and the formation of a thermal strain layer to produce wafers having a decreased incidence of defects and a balanced thermal strain. The wafers produced thereby are also disclosed.

582969

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