G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 13/38 (2006.01) G06F 12/08 (2006.01) G06F 12/10 (2006.01) G06F 13/364 (2006.01)
Patent
CA 2058581
A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher clients, each of which is coupled to a separate system bus. The bus allows the cache controller to provide independent processor-side access to the cache and allows the bus watchers to handle functions related to bus-snooping. An arbiter is employed to allow the bus to be multiplexed between the bus watchers and cache controller . Flow control mechanisms are also employed to ensure that queues receiving packets or arbitration requests over the bus never overflow. A default grantee mechanism is employed to minimize the arbitration latency due to a request for the bus when the bus is idle.
Chang Jung-Herng
Cruz-Rios Jorge
Frailong Jean-Marc
Lee Douglas B.
Liencres Bjorn
Riches Mckenzie & Herbert Llp
Sun Microsystems Inc.
Xerox Corporation
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